Si5351 has output channel up to 8 and each output has one Multisynth divider (MS). Please note MS0 to MS5 can support fractional and integer divider (from 8~900) while MS6 and MS7 only support integer divider (even integer divider from 6~254) (please refer to AN619 for detail information).
In addition to 8-channel version (20 QFN package), Si5351 also has 3-channel version (10MSOP package) and 4-channel version (16QFN package). The MS of 3-channel version is from MS0 to MS2 normally for CLK0 to CLK2. While please pay attention to mapping relationship between output and MS divider for 4-channel version. MS divider of CLK0/CLK1/CLK2 and CLK3 is MS1/MS2/MS5 and MS7. This leads to CLK3 min frequency can’t as low as 2.5KHz like CLK0/1/2. 18.75KHz is the min output frequency for CLK3 for 3-channel version.
The Low power LVPECL in Si5330x and Si5331x is pseudo-LVPECL which has different driver constructure with LVPECL and there is different termination for low power LVPECL. Please refer to below as DC coupling and AC coupling termination for low power LVPECL.
The termination of LVPECL please refer to http://www.ma3jooq.com/community/timing/knowledge-base.entry.html/2019/01/17/lvpecl_output_driver-BkN2
1.?A input clock or crystal should be valid before you write a new configuration (register map) to the RAM of Si5338
2. Writing new?values to the IC should follow read-modify-write process via write-allowed mask. Here is AN428 and source code about programming.
3. I2C timing:?
Hold Time?START?Condition tHD:STA should bigger than 4us for standard mode and 0.6us for fast mode.
Data Hold Time?tHD:DAT?should bigger than 100ns for standard mode?fast mode.
4. If you simulate I2C via FPGA,? please configure SDA to inout. Set SDA as output when write data, and Set SDA as input when ACK send to FPGA.
If you’re not able to communicate to your module, neither over the serial interface nor over the network, possibly due to installing the wrong update file. It requires that you use the Commander program, that you can connect to the module’s serial port and that you have access to the module’s reset or can power cycle the device.?
Please be noted that keep serial connection when you power cycle or reset the device. If your device/system are powered by USB that is also a serial port, you cannot plug out/plug in USB cable to power cycle the device. Because the serial connection will also be disconnected when you plug out/plug in USB cable. Please separate Serial port and power supply or use a reset signal for this case.?
Since power supply limitation, sometimes we need convert CMOS signal level to meet receiver requirement. Such as 3.3V to 2.5V, 1.8V to 1.2V
Please refer to below interfacing from AN408 for this conversion.
This resistor attenuator network should consider device source impedance Rs (usually this information can be found in datasheet). The R1 and R2 calculation should consider below two items:
1. R2 parallel with R1+ Rs to get 50 ohms resistor for impedance matching.
2. R2 /(R1+Rs) equal to ratio of receiver swing/ source swing
Attachment is one excel tool to calculate R1 and R2 according to source/receiver level and source impedance
In the Si5395-91 & Si5345-40 devices, DCO mode is intended to be used within the range of +/-350ppm. It is possible to use DCO mode beyond this range, but it is important to be aware of the following caveats:
where Fvco is the VCO frequency, NDEN is the N-divider denominator, NNUM is the N-divider numerator, NNUM,DELTA is the value which the numerator is being incremented/decremented by per step, X is the net amount of steps applied, and R is the integer R-divider value. If DCO mode is operated within a narrow frequency range, Fout has an approximately linear relation to X. However, as the frequency range increases, Fout becomes increasingly nonlinear with respect to X. Consequently, the actual frequency step size will be significantly different from the desired step size as the N-divider is continually incremented/decremented.
The following are the recommended solutions to address the above issues:
For more details on DCO mode and FOTF, please refer to the following application notes:
The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.
Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.
Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.
*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.
Proper HCSL Termination Networks
Examples of Improper HCSL Termination Networks
In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.
An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.
It is okay to provide an active clock signal to an unused input if:
It is not- okay to provide an active clock signal to an unused input if:
Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.
A HCSL clock can be applied at IN2, IN1, or IN0 of Si5341. Regarding to the termination, just use an AC blocking cap in series with each input. This is present a high impedance to the PCB trace and should be what the customer needs since they have source side impedance matching. You can remove the 100 Ohm resistor between IN+ and IN- if the source is terminated properly.
Or you can put the 100 Ohm resistor on the other side of the AC coupling caps but keep the 100 Ohm resistor within 5 mm of the input pins.